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| W90N740 Reference Manual W90N740 32-Bit ARM7TDMI-Based Micro-Controller Reference Manual -1- Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes of W90N740-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Winbond Electronics Corp. -2- W90N740 Reference Manual Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ............................................................................................................ 4 FEATURES .................................................................................................................................... 4 BLOCK DIAGRAM ......................................................................................................................... 8 PIN CONFIGURATION .................................................................................................................. 9 4.1. Pin Assignment ..................................................................................................................... 10 PIN DESCRIPTION...................................................................................................................... 13 ELECTRICAL CHARACTERISTICS............................................................................................ 17 6.1. Absolute Maximum Ratings (To Be Added).......................................................................... 17 6.2. DC Characteristics ................................................................................................................ 18 6.2.1. Digital DC Characteristics (To Be Added) ...................................................................................18 6.2.2. USB Transceiver DC Characteristics (To Be Added) ..................................................................18 6.3. AC Characteristics ................................................................................................................ 19 6.3.1. EBI/SDRAM Interface AC Characteristics ...................................................................................19 6.3.2. EBI/External Master Interface AC Characteristics .......................................................................20 6.3.3. EBI/(ROM/SRAM/External I/O) AC Characteristics .....................................................................21 6.3.4. USB Transceiver AC Characteristics...........................................................................................22 6.3.5. EMC MII AC Characteristics........................................................................................................24 7. 8. 9. 10. PACKAGE DIAMENSION ............................................................................................................ 26 W90N740 REGISTERS MAPPING TABLE ................................................................................. 27 ORDERING INFORMATION........................................................................................................ 39 REVISION HISTORY ................................................................................................................... 39 -3- Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 1. GENERAL DESCRIPTION The W90N740 micro-controller is 16/32 bit, ARM7TDMI based RISC micro-controller for network as well as embedded applications. An integrated dual Ethernet MAC, the W90N740, is designed for use in broadband routers, wireless access points, residential gateways and LAN camera. The W90N740N is built around The ARM7TDMI CPU core designed by Advanced RISC Machines, Ltd. And achieves 80MHz under worse conditions. Its small size, fully static design is particularly suitable for cost-sensitive and power-sensitive applications. It designs as Harvard architecture by offering an 8Kbyte I-cache/SRAM and an 2K-byte D-cache/SRAM with flexible configuration and two way set associative structure to balance data movement between CPU and external memory. Four stages write buffer also improves latency for write operations. The external bus interface (EBI) controller provides single bus architecture, 8/16/32 bit data width to access external SDRAM, ROM/SRAM, flash memory and I/O devices. It achieves same frequency as CPU core to minimize latency if internal cache misses. Memory controller supports different kinds of SDRAM types and configurations to ease system design. The System Manager includes an internal 32bit system bus arbiter and a PLL clock controller. Generic I/O bus is easily served as PCMCIA-like interface for 802.11b wireless LAN connection. Two 10/100Mb MACs of Ethernet controller is built in to reduce total system cost and increase performance between WAN and LAN port. Either MII or RMII of MAC is selected for external 10/100 PHY chip to design for varieties of applications. A powerful NAT accelerator (Patent Pending) between LAN and WAN reduces the software loading of CPU and speeds up performance between LAN and WAN. W90N740 integrates root hub of USB 1.1 host controller with one port transceiver and uses additional port with external transceiver if necessary, which can add valuable functions like flash disk, printer server, Bluetooth device via USB port. The important peripheral functions include one full wired high speed UART channel, 2-Channel GDMA, one watch-dog timer, two 24-bit timers with 8-bit prescale, 20 programmable I/O ports, and an advanced interrupt controller. 2. FEATURES Architecture * Highly-integrated system for embedded Ethernet applications * Powerful ARM7TDMI core and fully 16/32-bit RISC architecture * Big /Little-Endian mode supported * Cost-effective JTAG-based debug solution System Manager * System memory map & on-chip peripherals memory map * The data bus width of external memory address & data bus connection with external memory * Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode * Power-On setting * On-Chip PLL module control & Clock select control -4- W90N740 Reference Manual External Bus Interface (EBI) * External I/O Control with 8/16/32 bit external data bus * Cost-effective memory-to-peripheral DMA interface * SDRAM Controller supports up to 2 external SDRAM & the maximum size of each device is 32MB * ROM/FLASH & External I/O interface * Support for PCMCIA 16-bit PC Card devices On-Chip Instruction and Data Cache * Two-way, Set-associative, 8K-byte I-cache and 2K-byte D-cache * Support for LRU (Least Recently Used) Protocol * Cache can be configured as an internal SRAM * Support Cache Lock function Ethernet MAC Controller (EMC) * IEEE 802.3 protocol engine with programmable MII or RMII interface for 10/100 Mbits/s * DMA engine with burst mode * 256 bytes transmit & 256 bytes receive FIFO for MAC protocol engine and DMA access * Built-in 16 entry CAM Address Register * Support long frame (more than 1518 bytes) and short frame (less than 64 bytes) * Re-transmit (during collision) the frame without DMA access * Half or full duplex function option * Support Station Management for external PHY * On-Chip Pad generation NAT Accelerator (Patent Pending) * Hardware acceleration on IP address / port number look up and replacement for network address translation, including MAC address translation * Provide 64 entries of translation table * Support TCP / UDP packets GDMA Controller * 2 Channel GDMA for memory-to-memory data transfers without CPU intervention * Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers * Supports 4-data burst mode to boost performance * Support external GDMA request Publication Release Date: May 9, 2003 Revision A2 -5- W90N740 Reference Manual USB Host Controller * USB 1.1 compatible * Open Host Controller Interface (OHCI) 1.0 compatible. * Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices. * Built-in DMA for real-time data transfer UART * One UART (serial I/O) blocks with interrupt-based operation * Full set of MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD) * Fully programmable serial-interface characteristics: * Break generation and detection * False start bit detection * Parity, overrun, and framing error detection * Full prioritized interrupt system controls Timers * Two programmable 24-bit timers with 8-bit pre-scalar * One programmable 24-bit Watch-Dog timer * One-short mode, period mode or toggle mode operation Programmable I/Os * 21 programmable I/O ports I* /O ports Configurable for Multiple functions Advanced Interrupt Controller (AIC) * 18 interrupt sources, including 4 external interrupt sources * Programmable normal or fast interrupt mode (IRQ, FIQ) * Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources * Programmable as either low-active or high-active for 4 external interrupt sources * Priority methodology is encoded to allow for interrupt daisy-chaining * Automatically mask out the lower priority interrupt during interrupt nesting GPIO Controller * Programmable as an input or output pin -6- W90N740 Reference Manual On-Chip PLL * One PLL for both CPU and USB host controller * The external clock can be multiplied by on-chip PLL to provide high frequency system clock * Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred. Operation Voltage Range * 2.7 - 3.6 V for IO Buffer * 1.62 - 1.98 V for Core Logic Operation Temperature Range * 0 - 70 Degree C Operating Frequency * 80 MHz (default) Package Type * 176-pin LQFP -7- Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 3. BLOCK DIAGRAM W90N740 TDMI Bus JTAG ICE ARM7TDMI Wrapper 8K-Byte I Cache 2K-Byte D Cache Cache Controller PLL Clock Controller AHB Arbiter UART COM Port AHB Decoder SDRAM EBI Bus External Bus Controller ROM Flash RAM PCMCIA IO Dev APB Bridge Interrupt Controller External Interrupts AHB Bus APB Bus TIMER x2 GDMA Controller WDT GPIO USB Device USB Host Controller Ethenet MAC Controller 0 NAT Accelerator Ethenet MAC Controller 1 PHY PHY Fig 3.1 W90N740 Functional Block Diagram -8- W90N740 Reference Manual 4. PIN CONFIGURATION GP17/nIRQ0 GP18/nIRQ1 GP19/nIRQ2 GP20/nIRQ3 GP5/nRTS GP6/nCTS GP10/TxD GP11/RxD VDD33 MDC0 MDIO0 TX0_EN VSS33 TX0D0 TX0D1 TX0D2 TX0D3 TX0_CLK COL0 CRS0 RX0_CLK RX0D0 VDD18 VSS18 RX0D1 RX0D2 RX0D3 RX0_DV RX0_ERR VDD33 XTAL EXTAL VSS33 RX1_ERR RX1_CLK RX1_DV RX1D0 RX1D1 RX1D2 RX1D3 AVDD18 AVSS18 DVDD18 DVSS18 175 170 165 160 155 150 145 140 135 130 5 TX1D0 TX1D1 TX1D2 TX1D3 TX1EN COL1 CRS1 MDIO1 VSS33 MDC1 TX1CLK VDD33 GP0 GP1 GP2 GP3 GP12/nWDOG GP13/TIMER0 GP14/TIMER1 TMS TDI VDD18 VSS18 TDO TCK nTRST nRESET GP15/nXDACK GP16/nXDREQ EMACK EMREQ nWAIT VDD33 nOE VSS33 nECS0 nECS1 nECS2 nECS3 nBTCS nSCS0 nSCS1 SDQM0 SDQM1 125 10 120 15 20 W90N740 176-Pin LQFP 115 110 25 105 30 100 35 95 40 90 50 55 60 65 70 75 80 85 USBVDD DP DN USBVSS GP9/nDSR GP8/nDTR GP7/nCD GP4/nRI D31 D30 D29 D28 D27 D26 VSS33 D25 VDD33 D24 D23 VDD18 VSS18 D22 D21 D20 D19 D18 D17 D16 D15 D14 VSS33 D13 VDD33 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 VSS33 D0 VDD33 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 VSS33 A13 VDD33 A12 VDD18 VSS18 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS33 MCLK VDD33 nSCAS nSRAS nSWE MCKE NC NC SDQM3 SDQM2 Fig 4.1 176-Pin LQFP Pin Diagram -9- Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 4.1. Pin Assignment PIN NAME Clock & Reset EXTAL XTAL MCLK nRESET TAP Interface TCK TMS TDI TDO nTRST External Bus Interface A [24:22] A [21:0] D [31:16] D [15:0] nWBE [3:0]/ SDQM [3:0] nSCS[1:0] NSRAS NSCAS NSWE MCKE NC NC EMREQ EMACK nWAIT NBTCS nECS[3:0] NOE 25 20 21 24 26 ( 78 pins ) 84-82 81-74,72,70, 67-56 124-119,117, 115-114,111-105 104-103,101, 99-88,86 46-43 42,41 51 52 50 49 48 47 31 30 32 40 39-36 34 164 163 54 27 ( 5 pins ) 176-PIN LQFP ( 4 pins ) - 10 - W90N740 Reference Manual Pins Assignment, Continued PIN NAME Ethernet Interface (0) MDC0 MDIO0 COL0 / CRS0 / R1B_CRSDV TX0_CLK TX0D [3:0] / R1B_TXD [1:0], R0_TXD [1:0] TX0_EN / R0_TXEN RX0_CLK / R0_REFCLK RX0D [3:0] / R1B_RXD [1:0], R0_RXD [1:0] RX0_DV / R0_CRSDV RX0_ERR Ethernet Interface (1) MDC1 MDIO1 COL1 CRS1 TX1_CLK TX1D [3:0] / R1A_TX [1:0] TX1_EN /R1A_TXEN RX1_CLK / R1A_REFCLK RX1D [3:0] / R1A_RXD [1:0] RX1_DV / R1A_CRSDV RX1_ERR / R1A_RXERR 176-PIN LQFP ( 17 pins ) 142 143 151 152 150 149-146 144 153 159-157,154 160 161 ( 17 pins ) 10 8 6 7 11 4-1 5 167 172-169 168 166 - 11 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual Pins Assignment, Continued NAME USB Interface DP DN Miscellaneous GP [20:17] / nIRQ [3:0] GP16 / nXDREQ GP15 /nXDACK GP14 / TIMER1/ SPEED GP13 / TIMER0/ STDBY GP12 /nWDOG GP11 /RxD GP10 /TxD GP9/nDSR/nTOE GP8 /nDTR/FSE0 GP7 /nCD / VO GP6 /nCTS/ VM GP5 /nRTS/ VP GP4 /nRI / RCV GP [3:0] 29 28 19 18 17 140 139 128 127 126 138 137 125 16-13 131 130 ( 21 pins ) 136-133 176-PIN LQFP ( 2 pins ) Name Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 176-Pin LQFP (32 pins) 22,69,113,155 23,68,112,156 12,33,53,71,85, 100,116,141,162 9,35,55,73,87,102,118,145 ,165 132 129 175 176 173 174 - 12 - W90N740 Reference Manual 5. PIN DESCRIPTION PIN NAME System Clock & Reset EXTAL XTAL MCLK nRESET TAP Interface TCK TMS TDI TDO nTRST External Bus Interface A [24:22] A [21:0] D [31:16] D [15:0] nWBE [3:0]/ SDQM [3:0] nSCS [1:0] nSRAS nSCAS nSWE MCKE NC NC EMREQ EMACK nWAIT nBTCS nECS [3:0] nOE O IO IO IO IO O O O O O ID O External Master Bus Request ID O IU O IO O This is used to request external bus. When EMACK active, indicates the bus grants the bus, chip drives all the output pins of the external bus to high impedance. External Bus Acknowledge External Wait, active-low This pin indicates that the external devices need more active cycle during access operation. ROM/Flash Chip Select, active-low External I/O Chip Select, active-low. ROM/Flash, External Memory Output Enable, active-low Address Bus (MSB) of external memory and IO devices Address Bus of external memory and IO devices Data Bus (MSB) of external memory and IO device, internal pull-up with 70K ohm. Data Bus (LSB) of external memory and IO device Write Byte Enable for specific device(nECS[3:0]), Data input/output Mask signal for SDRAM (nSCS[1:0]), active-low SDRAM chip select for two external banks, active-low. Row Address Strobe for SDRAM, active-low Column Address Strobe for SDRAM, active-low SDRAM Write Enable, active-low SDRAM Clock Enable, active-high ID IU IU O IU JTAG Clock, internal pull-down with 58K ohm JTAG Mode Select, internal pull-up with 70K ohm JTAG Data in, internal pull-up with 70K ohm JTAG Data out JTAG Reset, active-low, internal pull-up with 70K ohm I O O I External Clock / Crystal Input Crystal Output System Master Clock Out, SDRAM clock System Reset, active-low IO TYPE DESCRIPTION - 13 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual Pins Description, Continued PIN NAME IO TYPE DESCRIPTION Ethernet Interface (0) MDC0 MDIO0 COL0 CRS0 TX0_CLK O IO I I I MII Management Data Clock for Ethernet 0. It is the reference clock of MDIO0. Each MDIO0 data will be latched at the rising edge of MDC0 clock. MII Management Data I/O for Ethernet 0. It is used to transfer MII control and status information between PHY and MAC. Collision Detect for Ethernet 0 in MII mode. This shall be asserted by PHY upon detecting a collision happened over the medium. It will be asserted and lasted until collision condition vanishes. Carrier Sense for Ethernet 0 in MII mode. Transmit Data Clock for Ethernet 0 in MII mode. TX0_CLK is driven by PHY and provides the timing reference for TX0_EN and TX0D. The clock will be 25MHz or 2.5 MHz. Transmit Data bus (4-bit) for Ethernet 0 in MII mode. The nibble transmit data bus is synchronized with TX0_CLK. It should be latched by PHY at the rising edge of TX0_CLK. In RMII mode, TX0D [1:0] are used as R0_TXD [1:0],2-bit Transmit Data bus for Ethernet 0. Transmit Enable for Ethernet 0 in MII. It indicates the transmit activity to external PHY. It will be synchronized with TX0_CLK. O In RMII mode, R0_TXEN shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented. Of course, it is synchronized with R0_REFCLK. Receive Data Clock for Ethernet 0 in MII mode When it is used as a received clock pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The minimum duty cycle at its high or low state should be 35% of the nominal period for all conditions. In RMII mode, this pin is used as R0_REFCLK, Reference Clock; The clock shall be 50MHz +/- 50 ppm with minimum 35% duty cycle at high or low state. Receive Data bus (4-bit) for Ethernet 0 in MII mode. They are driven by external PHY, and should be synchronized with RX0_CLK and valid only when RX0_DV is valid. In RMII mode, RX0D [1:0] are used as R0_RXD [1:0], 2-bit Receive Data bus for Ethernet 0. Receive Data Valid for Ethernet 0 in MII mode. It will be asserted when received data is coming and present, and de-asserted at the end of the frame. RX0_DV / R0_CRSDV I In RMII mode, this pin is used as the R0_CRSDV, Carrier Sense / Receive Data Valid for Ethernet 0. The R0_CRSDV shall be asserted by PHY when the receive medium is nonidle. Loss of carrier shall result in the de-assertion of R0_CRSDV synchronous to the cycle of R0_REFCLK, and only on nibble boundaries. Receive Data Error for Ethernet 0 in MII mode. It indicates a data error detected by PHY. The assertion should be lasted for longer than a period of RX0_CLK. When RX0_ERR is asserted, the MAC will report a CRC error. TX0D [3:0] / R0_TXD [1:0] O TX0_EN / R0_TXEN RX0_CLK / R0_REFCLK I RX0D [3:0] / R0_RXD [1:0] I RX0_ERR I - 14 - W90N740 Reference Manual Pins Description, Continued PIN NAME Ethernet Interface (1) MDC1 MDIO1 COL1 CRS1 TX1_CLK O IOU IU IU IU MII Management Data Clock for Ethernet 1. It is the reference clock of MDIO1. Each MDIO1 data will be latched at the rising edge of MDC1 clock. MII Management Data I/O for Ethernet 1. It is used to transfer MII control and status information between PHY and MAC. Collision Detect for Ethernet 1 in MII mode. This shall be asserted by PHY upon detecting a collision happened over the medium. It will be asserted and lasted until collision condition vanishes. Carrier Sense for Ethernet 1 in MII mode. Transmit Data Clock for Ethernet 1 in MII mode, TX1_CLK is driven by PHY and provides the timing reference for TX1_EN and TX1D. The clock will be 25MHz or 2.5 MHz. Transmit Data bus (4-bit) for Ethernet 1 in MII mode. The nibble transmit data bus is synchronized with TX1_CLK. It should be latched by PHY at the rising edge of TX1_CLK. In RMII mode, TX1D [1:0] are used as R1A_TXD [1:0], 2-bit Transmit Data bus for Ethernet 1. O Transmit Enable for Ethernet 1 in MII and RMII mode. It indicates the transmit activity to external PHY. It will be synchronized with TX1_CLK in MII mode. Receive Data Clock for Ethernet 1 in MII mode. When it is used as a received clock pin, it is from PHY. The clock will be either 25 MHz or 2.5 MHz. The minimum duty cycle at its high or low state should be 35% of the nominal period for all conditions. In RMII mode, this pin is used as R1A_REFCLK. The clock shall be 50MHz +/-50 ppm with minimum 35% duty cycle at high or low state. Receive Data bus (4-bit) for Ethernet 1 in MII mode. They are driven by external PHY, and should be synchronized with RX1_CLK and valid only when RX1_DV is valid. In RMII mode, RX1D [1:0] are used as R1A_RXD [1:0], 2-bit Receive Data bus for Ethernet 1. Receive Data Valid for Ethernet 1 in MII mode. It will be asserted when received data is coming and present, and de-asserted at the end of the frame. RX1_DV/ R1A_CRSDV IU In RMII mode, this pin is used as the R1A_CRSDV, Carrier Sense / Receive Data Valid for Ethernet 1. The R1A_CRSDV shall be asserted by PHY when the receive medium is non-idle. Loss of carrier shall result in the de-assertion of R1A_CRSDV synchronous to the cycle of R1A_REFCLK, and only on nibble boundaries. Receive Data Error for Ethernet 1 in MII and RMII mode. It indicates a data error detected by PHY. The assertion should be lasted for longer than a period of RX0_CLK. When RX0_ERR is asserted, the MAC will report a CRC error. IO TYPE DESCRIPTION TX1D [3:0] / R1A_TXD [1:0] O TX1_EN/ R1A_TXEN RX1_CLK / R1A_REFCLK IU RX1D [3:0] / R1A_RXD[1:0] IU RX1_ERR / R1A_RXERR IU - 15 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual Pins Description, Continued NAME USB Interface DP DN Miscellaneous GP[20:17] / nIRQ[3:0] GP16 / nXDREQ GP15 /nXDACK GP14 / TIMER1/SPEED GP13 / TIMER0/STDBY GP12 /nWDOG GP11 /RxD GP10 /TxD GP9/nDSR/nTOE GP8 /nDTR/FSE0 GP7 /nCD /VO GP6 /nCTS/ VM GP5 /nRTS/ VP GP4 /nRI /RCV GP[3:0] Power/Ground VDD18 VSS18 VDD33 VSS33 USBVDD USBVSS DVDD18 DVSS18 AVDD18 AVSS18 P G P G P G P G P G Core Logic power (1.8V) Core Logic ground (0V) IO Buffer power (3.3V) IO Buffer ground (0V) USB power (3.3V) USB ground (0V) PLL Digital power (1.8V) PLL Digital ground (0V) PLL Analog power (1.8V) PLL Analog ground (0V) IO IO IO IO External Interrupt Request or General Purpose I/O External DMA Request or General Purpose I/O External DMA Acknowledge or General Purpose I/O Timer 1 or General Purpose I/O. This pin is also used as SPEED, Speed mode control for external USB transceiver Timer 0 or General Purpose I/O. This pin is also used as STDBY, StandBy control for external USB transceiver Watchdog Timer Timeout Flag (active-low) or General Purpose I/O UART Receive Data or General Purpose I/O UART Transmit Data or General Purpose I/O UART Receive Clock or General Purpose I/O. This pin is also used as nTOE, Output Enable control (active-low) for external USB transceiver. UART Transmit Clock or General Purpose I/O. This pin is also used as SE0, Differential Data Transceiver Output for external USB transceiver. UART Carrier Detector or General Purpose I/O. This pin is also used as VO, Data Output for external USB transceiver. UART Clear to Send or General Purpose I/O. This pin is also used as VM, Data Negative (Minus) Input for external USB receiver. UART Ready to Send or General Purpose I/O. This pin is also used as VP, Data Positive Input for external USB receiver. UART Ring Indicator or General Purpose I/O. This pin is also used as RCV, Difference Receiver Input. General Purpose I/O. IO IO Differential Positive USB IO signal Differential Negative (Minus) USB IO signal IO TYPE DESCRIPTION IO IO IO IO IOU IOU IOU IOU IOU IOU IOU - 16 - W90N740 Reference Manual 6. ELECTRICAL CHARACTERISTICS 6.1. Absolute Maximum Ratings (To Be Added) Ambient Temperature ............................................................................. Storage Temperature ............................................................................ Voltage on Any Pin ............................................................................... Power Supply Voltage (Core logic) ............................................................ Power Supply Voltage (IO Buffer) ............................................................. Injection Current (latch-up testing) ......................................................... Crystal Frequency .................................................................................... - 17 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 6.2. DC Characteristics 6.2.1. Digital DC Characteristics (To Be Added) SYMBOL PARAMETER CONDITION MIN. MAX. UNIT VDD33/ USBVDD VDD18/ DVDD18/ AVDD18 VIL VIH VT+ VTVOL VOH ICC IIH IIL IIHP IILP IIHD IILD Power Supply V Power Supply Input Low Voltage Input High Voltage Schmitt Trigger positive-going threshold Schmitt trigger negative-going threshold Output Low Voltage Output High Voltage Supply Current Input High Current Input Low Current Input High Current (pull-up) Input Low Current (pull-up) Input High Current (pull-down) Input Low Current (pull-down) V V V V V V V mA A A A A A A 6.2.2. USB Transceiver DC Characteristics (To Be Added) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDI VCM VSE VOL VOH VCRS ZDRV CIN Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Static Output Low Voltage Static Output High Voltage Output Signal Crossover Voltage Driver Output Resistance Pin Capacitance V V V V V V pF - 18 - W90N740 Reference Manual 6.3. AC Characteristics 6.3.1. EBI/SDRAM Interface AC Characteristics MCLK TDSU D[31:0] 1.5V 1.5V TDH 1.5V Input Valid MCLK 1.5V TDO Output Delay 1.5V Output Valid SYMBOL PARAMETER MIN. MAX. UNIT TDSU TDH TDO D [31:0] Setup Time D [31:0] Hold Time D [31:0], A [24:0], nSCS [1:0], SDQM [3:0], CKE, nSWE, nSRAS, nSCAS nS nS nS - 19 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 6.3.2. EBI/External Master Interface AC Characteristics MCLK EMREQ TEMSU TEMAO TEMH EMACK TEMAO SYMBOL DESCRIPTION MIN MAX UNIT TEMSU TEMH TEMAO EMREQ Setup Time EMREQ Hold Time EMACK Output Delay Time nS nS nS - 20 - W90N740 Reference Manual 6.3.3. EBI/(ROM/SRAM/External I/O) AC Characteristics MCLK TNECSO nECS[3:0] TADDO A[24:0] Address Valid TNECSO nOE TNOEO TNOEO TDSU TDH R Data D[31:0] nWAIT TNWASU TNWAH TNWBO TDO D[31:0] Write Data Vaild nWBE[3:0] TNWBO (To Be Added) SYMBOL DESCRIPTION MIN. MAX. UNIT TADDO TNCSO TNOEO TNWBO TDH TDSU TDO TNWASU TNWAH Address Output Delay Time ROM/SRAM/Flash or External I/O Chip Select Delay Time ROM/SRAM or External I/O Bank Output Enable Delay ROM/SRAM or External I/O Bank Write Byte Enable Delay Read Data Hold Time Read Data Setup Time Write Data Output Delay Time (SRAM or External I/O) External Wait Setup Time External Wait Hold Time nS nS nS nS nS nS nS nS nS - 21 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 6.3.4. USB Transceiver AC Characteristics Rise Time CL Differential Data Lines 90% 10% 90% Fall Time 10% CL Full Speed: 4 to 20ns at CL = 50pF tR tF Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Data Signal Rise and Fall Time TPERIOD Differential Data Lines Crossover Points Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2 Differential Data Jitter TPERIOD Differential Data Lines Crossover Point Crossover Point Extended Diff. Data to SE0 Skew N * TPERIOD + TDEOP Source EOP Width: TEOPT Receiver EOP Width: TEOPR1, TEOPR2 Differential to EOP Transition Skew and EOP Width - 22 - W90N740 Reference Manual TPERIOD Differential Data Lines T JR Consecutive Transitions N * TPERIOD + T JR1 Paired Transitions N * TPERIOD + TJR2 T JR1 TJR2 Receiver Jitter Tolerance USB Transceiver AC Characteristics (To Be Added) SYMBOL DESCRIPTION CONDITIONS MIN. MAX. UNIT TR TF TRFM TDRATE TDJ1 TDJ2 TEOPT TDEOP TJR1 TJR2 TEOPR1 TEOPR2 Rise Time Fall Time Rise/Fall Time Matching Full Speed Data Rate Source Differential Driver Jitter To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver Data Jitter Tolerance To Next Transition For Paired Transitions EOP Width at Receiver Must Reject as EOP Must Accept as EOP nS nS % Mbps nS nS nS nS nS - 23 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 6.3.5. EMC MII AC Characteristics The signal timing characteristics conforms to the guidelines specified in IEEE Std. 802.3. TX_CLK TX_D [3:0] TX_EN TX_ERR TTXO Valid Transmit Signal Timing Relationships at MII RX_CLK RX_D [3:0] RX_DV RX_ERR TRXSU TRXH VALID INPUT Receive Signal Timing Relationships at MII (To Be Added) SYMBOL DESCRIPTION MIN. MAX. UNIT TTXO TRXSU TRXH Transmit Output Delay Time Receive Setup Time Receive Hold Time nS nS nS - 24 - W90N740 Reference Manual Continued MDC TMDSU TMDH MDIO VALID INPUT MDIO Read From PHY Timing MDC TMDO Valid MDIO MDIO Write to PHY Timing (To Be Added) SYMBOL DESCRIPTION MIN. MAX. UNIT TMDO TMDSU TMDH MDIO Output Delay Time MDIO Setup Time MDIO Hold Time nS nS nS - 25 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual 7. PACKAGE DIAMENSION 176-Pin LQFP - 26 - W90N740 Reference Manual 8. W90N740 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written System Manager Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE PDID ARBCON PLLCON CLKSEL 0xFFF0.0000 0xFFF0.0004 0xFFF0.0008 0xFFF0.000C R R/W R/W R/W Product Identifier Register Arbitration Control Register PLL Control Register Clock Select Register 0xX090.0740 0x0000.0000 0x0000.2F01 0x0000.3FX8 EBI Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE EBICON ROMCON SDCONF0 SDCONF1 SDTIME0 SDTIME1 EXT0CON EXT1CON EXT2CON EXT3CON CKSKEW 0xFFF0.1000 0xFFF0.1004 0xFFF0.1008 0xFFF0.100C 0xFFF0.1010 0xFFF0.1014 0xFFF0.1018 0xFFF0.101C 0xFFF0.1020 0xFFF0.1024 0xFFF0.1F00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W EBI control register ROM/FLASH control register SDRAM bank 0 configuration register SDRAM bank 1 configuration register SDRAM bank 0 timing control register SDRAM bank 1 timing control register External I/O 0 control register External I/O 1 control register External I/O 2 control register External I/O 3 control register Clock skew control register 0x0001.0000 0x0000.0XFC 0x0000.0800 0x0000.0800 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0xXXXX.0038 Cache Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAHCNF CAHCON CAHADR 0xFFF0.2000 0xFFF0.2004 0xFFF0.2008 R/W R/W R/W Cache configuration register Cache control register Cache address register 0x0000.0000 0x0000.0000 0x0000.0000 - 27 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual EMC 0 Control registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAMCMR_0 CAMEN_0 CAM1M_0 CAM1L_0 CAM2M_0 CAM2L_0 CAM3M_0 CAM3L_0 CAM4M_0 CAM4L_0 CAM5M_0 CAM5L_0 CAM6M_0 CAM6L_0 CAM7M_0 CAM7L_0 CAM8M_0 CAM8L_0 CAM9M_0 CAM9L_0 CAM10M_0 CAM10L_0 CAM11M_0 CAM11L_0 CAM12M_0 CAM12L_0 CAM13M_0 CAM13L_0 CAM14M_0 CAM14L_0 0xFFF0.3000 0xFFF0.3004 0xFFF0.3008 0xFFF0.300C 0xFFF0.3010 0xFFF0.3014 0xFFF0.3018 0xFFF0.301C 0xFFF0.3020 0xFFF0.3024 0xFFF0.3028 0xFFF0.302C 0xFFF0.3030 0xFFF0.3034 0xFFF0.3038 0xFFF0.303C 0xFFF0.3040 0xFFF0.3044 0xFFF0.3048 0xFFF0.304C 0xFFF0.3050 0xFFF0.3054 0xFFF0.3058 0xFFF0.305C 0xFFF0.3060 0xFFF0.3064 0xFFF0.3068 0xFFF0.306C 0xFFF0.3070 0xFFF0.3074 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CAM Command Register CAM enable register CAM1 Most Significant Word Register CAM1 Least Significant Word Register CAM2 Most Significant Word Register CAM2 Least Significant Word Register CAM3 Most Significant Word Register CAM3 Least Significant Word Register CAM4 Most Significant Word Register CAM4 Least Significant Word Register CAM5 Most Significant Word Register CAM5 Least Significant Word Register CAM6 Most Significant Word Register CAM6 Least Significant Word Register CAM7 Most Significant Word Register CAM7 Least Significant Word Register CAM8 Most Significant Word Register CAM8 Least Significant Word Register CAM9 Most Significant Word Register CAM9 Least Significant Word Register CAM10 Most Significant Word Register CAM10 Least Significant Word Register CAM11 Most Significant Word Register CAM11 Least Significant Word Register CAM12 Most Significant Word Register CAM12 Least Significant Word Register CAM13 Most Significant Word Register CAM13 Least Significant Word Register CAM14 Most Significant Word Register CAM14 Least Significant Word Register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 - 28 - W90N740 Reference Manual EMC 0 Control registers Map, continued REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAM15M_0 CAM15L_0 CAM16M_0 CAM16L_0 MIEN_0 MCMDR_0 MIID_0 MIIDA_0 MPCNT_0 DMA REGISTERS TXDLSA_0 RXDLSA_0 DMARFC_0 TSDR_0 RSDR_0 FIFOTHD_0 0xFFF0.309C 0xFFF0.30A0 0xFFF0.30A4 0xFFF0.30A8 0xFFF0.30AC 0xFFF0.30B0 R/W R/W Transmit Descriptor Link List Start Address 0xFFFF.FFFC register Receive Descriptor Link List Start Address 0xFFFF.FFFC register 0x0000.0800 Undefined Undefined 0x0000.0101 Transmit Start Demand Register Receive Start Demand Register 0xFFF0.3078 0xFFF0.307C 0xFFF0.3080 0xFFF0.3084 0xFFF0.3088 0xFFF0.308C 0xFFF0.3090 0xFFF0.3094 0xFFF0.3098 R/W R/W R/W R/W CAM15 Most Significant Word Register CAM15 Least Significant Word Register CAM16 Most Significant Word Register CAM16 Least Significant Word Register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 MAC REGISTERS R/W MAC Interrupt Enable Register R/W MAC Command Register R/W MII Management Data Register R/W MII Management Data Control and Address 0x0090.0000 Register 0x0000.7FFF R/W Missed Packet counter register R/W DMA Receive Frame Control Register W W R/W FIFO Threshold Adjustment Register - 29 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual EMC 0 Status Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MAC REGISTERS MISTA_0 MGSTA_0 MRPC_0 MRPCC_0 MREPC_0 0xFFF0.30B4 R/W MAC Interrupt Status Register 0xFFF0.30B8 R/W MAC General Status Register 0xFFF0.30BC 0xFFF0.30C0 0xFFF0.30C4 R R R MAC Receive Pause count register MAC Receive Pause Current Count Register MAC Remote pause count register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 DMA REGISTERS DMARFS_0 0xFFF0.30C8 R/W DMA Receive Frame Status Register CTXDSA_0 CTXBSA_0 0xFFF0.30CC 0xFFF0.30D0 R R R R Current Transmit Descriptor Start Address Register Current Transmit Buffer Start Address Register Current Receive Descriptor Start Address Register Current Receive Buffer Start Address Register CRXDSA_0 0xFFF0.30D4 CRXBSA_0 0xFFF0.30D8 - 30 - W90N740 Reference Manual EMC 1 Control Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAMCMR_1 CAMEN_1 CAM1M_1 CAM1L_1 CAM2M_1 CAM2L_1 CAM3M_1 CAM3L_1 CAM4M_1 CAM4L_1 CAM5M_1 CAM5L_1 CAM6M_1 CAM6L_1 CAM7M_1 CAM7L_1 CAM8M_1 CAM8L_1 CAM9M_1 CAM9L_1 CAM10M_1 CAM10L_1 CAM11M_1 CAM11L_1 CAM12M_1 CAM12L_1 CAM13M_1 CAM13L_1 0xFFF0.3800 0xFFF0.3804 0xFFF0.3808 0xFFF0.380C 0xFFF0.3810 0xFFF0.3814 0xFFF0.3818 0xFFF0.381C 0xFFF0.3820 0xFFF0.3824 0xFFF0.3828 0xFFF0.382C 0xFFF0.3830 0xFFF0.3834 0xFFF0.3838 0xFFF0.383C 0xFFF0.3840 0xFFF0.3844 0xFFF0.3848 0xFFF0.384C 0xFFF0.3850 0xFFF0.3854 0xFFF0.3858 0xFFF0.385C 0xFFF0.3860 0xFFF0.3864 0xFFF0.3868 0xFFF0.386C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CAM Command Register CAM enable register CAM1 Most Significant Word Register CAM1 Least Significant Word Register CAM2 Most Significant Word Register CAM2 Least Significant Word Register CAM3 Most Significant Word Register CAM3 Least Significant Word Register CAM4 Most Significant Word Register CAM4 Least Significant Word Register CAM5 Most Significant Word Register CAM5 Least Significant Word Register CAM6 Most Significant Word Register CAM6 Least Significant Word Register CAM7 Most Significant Word Register CAM7 Least Significant Word Register CAM8 Most Significant Word Register CAM8 Least Significant Word Register CAM9 Most Significant Word Register CAM9 Least Significant Word Register CAM10 Most Significant Word Register CAM10 Least Significant Word Register CAM11 Most Significant Word Register CAM11 Least Significant Word Register CAM12 Most Significant Word Register CAM12 Least Significant Word Register CAM13 Most Significant Word Register CAM13 Least Significant Word Register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 - 31 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual REGISTER ADDRESS R/W DESCRIPTION RESET VALUE CAM REGISTERS CAM14M_1 CAM14L_1 CAM15M_1 CAM15L_1 CAM16M_1 CAM16L_1 MIEN_1 MCMDR_1 MIID_1 MIIDA_1 MPCNT_1 0xFFF0.3870 0xFFF0.3874 0xFFF0.3878 0xFFF0.387C 0xFFF0.3880 0xFFF0.3884 0xFFF0.3888 0xFFF0.388C 0xFFF0.3890 0xFFF0.3894 0xFFF0.3898 R/W R/W R/W R/W R/W R/W CAM14 Most Significant Word Register CAM14 Least Significant Word Register CAM15 Most Significant Word Register CAM15 Least Significant Word Register CAM16 Most Significant Word Register CAM16 Least Significant Word Register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0090.0000 0x0000.7FFF MAC REGISTERS R/W MAC Interrupt Enable Register R/W MAC Command Register R/W MII Management Data Register R/W MII Management Data Control and Address Register R/W Missed Packet counter register DMA REGISTERS TXDLSA_1 RXDLSA_1 DMARFC_1 TSDR_1 RSDR_1 FIFOTHD_1 0xFFF0.389C 0xFFF0.38A0 0xFFF0.38A4 0xFFF0.38A8 0xFFF0.38AC 0xFFF0.38B0 R/W R/W Transmit Descriptor Link List Start Address 0xFFFF.FFFC register Receive Descriptor Link List Start Address 0xFFFF.FFFC register 0x0000.0800 Undefined Undefined 0x0000.0101 Transmit Start Demand Register Receive Start Demand Register R/W DMA Receive Frame Control Register W W R/W FIFO Threshold Adjustment Register - 32 - W90N740 Reference Manual EMC 1 Status Registers REGISTER ADDRESS R/W DESCRIPTION RESET VALUE MAC REGISTERS MISTA_1 MGSTA_1 MRPC_1 MRPCC_1 MREPC_1 DMARFS_1 CTXDSA_1 CTXBSA_1 CRXDSA_1 CRXBSA_1 0xFFF0.38B4 0xFFF0.38B8 0xFFF0.38BC 0xFFF0.38C0 0xFFF0.38C4 0xFFF0.38C8 0xFFF0.38CC 0xFFF0.38D0 0xFFF0.38D4 0xFFF0.38D8 R/W MAC Interrupt Status Register R/W MAC General Status Register R R R MAC Receive Pause count register MAC Receive Pause Current Count Register MAC Remote pause count register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 DMA REGISTERS R/W DMA Receive Frame Status Register R R R R Current Transmit Descriptor Start Address Register Current Receive Descriptor Start Address Register Current Receive Buffer Start Address Register Current Transmit Buffer Start Address Register 0x0000.0000 0x0000.0000 0x0000.0000 GDMA Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GDMA_CTL0 GDMA_SRCB0 GDMA_DSTB0 GDMA_TCNT0 GDMA_CSRC0 GDMA_CDST0 GDMA_CTCNT0 GDMA_CTL1 GDMA_SRCB1 GDMA_DSTB1 GDMA_TCNT1 GDMA_CSRC1 GDMA_CDST1 GDMA_CTCNT1 0xFFF0.4000 R/W Channel 0 Control Register 0xFFF0.4004 R/W Channel 0 Source Base Address Register 0xFFF0.4008 R/W Channel 0 Destination Base Address Register 0xFFF0.400C R/W Channel 0 Transfer Count Register 0xFFF0.4010 0xFFF0.4014 0xFFF0.4018 R R R Channel 0 Current Source Address Register Channel 0 Current Destination Address Register Channel 0 Current Transfer Count Register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0xFFF0.4020 R/W Channel 1 Control Register 0xFFF0.4024 R/W Channel 1 Source Base Address Register 0xFFF0.4028 R/W Channel 1 Destination Base Address Register 0xFFF0.402C R/W Channel 1 Transfer Count Register 0xFFF0.4030 0xFFF0.4034 0xFFF0.4038 R R R Channel 1 Current Source Address Register Channel 1 Current Destination Address Register Channel 1 Current Transfer Count Register - 33 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual USB Host Controller Registers Map REGISTER ADDRESS 0xFFF0.5000 0xFFF0.5004 0xFFF0.5008 0xFFF0.500C 0xFFF0.5010 0xFFF0.5014 0xFFF0.5018 0xFFF0.501C 0xFFF0.5020 0xFFF0.5024 0xFFF0.5028 0xFFF0.502C 0xFFF0.5030 0xFFF0.5034 0xFFF0.5038 0xFFF0.503C 0xFFF0.5040 0xFFF0.5044 0xFFF0.5048 0xFFF0.504C 0xFFF0.5050 0xFFF0.5054 0xFFF0.5058 R/W DESCRIPTION RESET VALUE OpenHCI Registers HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HCBulkCurrentED HcDoneHead HcFmInterval HcFrameRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus [1] HcRhPortStatus [2] R Host Controller Revision Register Host Controller Command Status Register 0x0000.0010 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 R/W Host Controller Control Register R/W R/W Host Controller Interrupt Status Register R/W Host Controller Interrupt Enable Register R/W Host Controller Interrupt Disable Register R/W R/W Host Controller Communication Area Register Host Controller Period Current ED Register Host Controller Control Current ED Register R/W Host Controller Control Head ED Register 0x0000.0000 R/W 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.2EDF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0628 0x0100.0002 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 R/W Host Controller Bulk Head ED Register R/W Host Controller Bulk Current ED Register R/W Host Controller Done Head Register R/W Host Controller Frame Interval Register R R Host Controller Frame Remaining Register Host Controller Frame Number Register Host Controller Low Speed Threshold Register Host Controller Root Hub Descriptor A Register Host Controller Root Hub Descriptor B Register R/W Host Controller Periodic Start Register R/W R/W R/W R/W Host Controller Root Hub Status Register R/W Host Controller Root Hub Port Status [1] R/W Host Controller Root Hub Port Status [2] - 34 - W90N740 Reference Manual NATA Registers Map REGISTER OFFSET R/W DESCRIPTION RESET VALUE NATA Control and Status Registers NATCMD NATCCLR0 NATCCLR1 NATCCLR2 NATCCLR3 NATCFG0 NATCFG1 . . . NATCFG63 EXMACM EXMACL INMACM INMACL 0xFFF0.6000 0xFFF0.6010 0xFFF0.6014 0xFFF0.6018 0xFFF0.601C 0xFFF0.6100 0xFFF0.6104 . . . R/W NAT Command Register W W W W NAT Counter 0 Clear Register NAT Counter 1 Clear Register NAT Counter 2 Clear Register NAT Counter 3 Clear Register 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 . . . 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 R/W NAT Entry 0 Configuration Register R/W NAT Entry 1 Configuration Register . . . . . . External MAC Address Most Significant Word Register External MAC Address Least Significant Word Register Internal MAC Address Most Significant Word Register Internal MAC Address Least Significant Word Register 0xFFF0.61FC R/W NAT Entry 63 Configuration Register 0xFFF0.6200 0xFFF0.6204 0xFFF0.6208 R/W R/W R/W 0xFFF0.620C R/W - 35 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual REGISTER OFFSET R/W DESCRIPTION RESET VALUE Address Lookup and Replacement Registers MASAD0 MASPN0 LSAD0 LSPN0 LSMAC0M LSMAC0L RSMAC0M RSMAC0L MASAD1 MASPN1 LSAD1 LSPN1 LSMAC1M LSMAC1L RSMAC1M RSMAC1L ... MASAD63 MASPN63 LSAD63 LSPN63 LSMAC63M LSMAC63L RSMAC63M RSMAC63L 0xFFF0.6800 0xFFF0.6804 0xFFF0.6808 0xFFF0.680C 0xFFF0.6810 0xFFF0.6814 0xFFF0.6818 0xFFF0.681C 0xFFF0.6820 0xFFF0.6824 0xFFF0.6828 0xFFF0.682C 0xFFF0.6830 0xFFF0.6834 0xFFF0.6838 0xFFF0.683C ... 0xFFF0.6FE0 0xFFF0.6FE4 0xFFF0.6FE8 0xFFF0.6FEC 0xFFF0.6FF0 0xFFF0.6FF4 0xFFF0.6FF8 0xFFF0.6FFC R/W NAT Masquerading IP Address Entry 0 R/W NAT Masquerading Port Number Entry 0 R/W Local Station IP Address Entry 0 R/W Local Station Port Number Entry 0 R/W R/W R/W R/W Local Station MAC Address Most Significant Word Register for Entry 0 Local Station MAC Address Least Significant Word Register for Entry 0 Remote Station MAC Address Most Significant Word Register for Entry 0 Remote Station MAC Address Least Significant Word Register for Entry 0 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 ... 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 R/W NAT Masquerading IP Address Entry 1 R/W NAT Masquerading Port Number Entry 1 R/W Local Station IP Address Entry 1 R/W Local Station Port Number Entry 1 R/W R/W R/W R/W ... Local Station MAC Address Most Significant Word Register for Entry 1 Local Station MAC Address Least Significant Word Register for Entry 1 Remote Station MAC Address Most Significant Word Register for Entry 1 Remote Station MAC Address Least Significant Word Register for Entry 1 ... R/W NAT Masquerading IP Address Entry 63 R/W NAT Masquerading Port Number Entry 63 R/W Local Station IP Address Entry 63 R/W Local Station Port Number Entry 63 R/W R/W R/W R/W Local Station MAC Address Most Significant Word Register for Entry 63 Local Station MAC Address Least Significant Word Register for Entry 63 Remote Station MAC Address Most Significant Word Register for Entry 63 Remote Station MAC Address Least Significant Word Register for Entry 63 - 36 - W90N740 Reference Manual UART Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE RBR THR IER DLL DLM IIR FCR LCR MCR LSR MSR TOR 0xFFF8.0000 0xFFF8.0000 0xFFF8.0004 0xFFF8.0000 0xFFF8.0004 0xFFF8.0008 0xFFF8.0008 0xFFF8.000C 0xFFF8.0010 0xFFF8.0014 0xFFF8.0018 0xFFF8.001C R W R/W R/W R/W R W R/W R/W R R R Receive Buffer Register (DLAB = 0) Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register MODEM Status Register Time Out Register Undefined Undefined 0x0000.0000 0x0000.0000 0x0000.0000 0x8181.8181 Undefined 0x0000.0000 0x0000.0000 0x6060.6060 0x0000.0000 0x0000.0000 Timer Control Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE TCR0 TCR1 TICR0 TICR1 TDR0 TDR1 TISR WTCR 0xFFF8.1000 0xFFF8.1004 0xFFF8.1008 0xFFF8.100C 0xFFF8.1010 0xFFF8.1014 0xFFF8.1018 0xFFF8.101C R/W R/W R/W R/W R R R/C R/W Timer Control Register 0 Timer Control Register 1 Timer Initial Control Register 0 Timer Initial Control Register 1 Timer Data Register 0 Timer Data Register 1 Timer Interrupt Status Register Watchdog Timer Control Register 0x0000.0005 0x0000.0005 0x0000.00FF 0x0000.00FF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 GPIO Controller Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE GPIO_CFG GPIO_DIR GPIO_DATAOUT GPIO_DATAIN DEBNCE_CTRL 0xFFF8.3000 0xFFF8.3004 0xFFF8.3008 0xFFF8.300C 0xFFF8.3010 R/W R/W R/W R R/W GPIO Configuration Register GPIO Direction Register GPIO Data Output Register GPIO Data Input Register De-bounce Control Register 0x0000.0000 0x0000.0000 0x0000.0000 Undefined 0x0000.0000 - 37 - Publication Release Date: May 9, 2003 Revision A2 W90N740 Reference Manual AIC Registers Map REGISTER ADDRESS R/W DESCRIPTION RESET VALUE AIC_SCR1 AIC_SCR2 AIC_SCR3 AIC_SCR4 AIC_SCR5 AIC_SCR6 AIC_SCR7 AIC_SCR8 AIC_SCR9 AIC_SCR10 AIC_SCR11 AIC_SCR12 AIC_SCR13 AIC_SCR14 AIC_SCR15 AIC_SCR16 AIC_SCR17 AIC_SCR18 AIC_IRSR AIC_IASR AIC_ISR AIC_IPER AIC_ISNR AIC_IMR AIC_OISR AIC_MECR AIC_MDCR AIC_SSCR AIC_SCCR AIC_EOSCR 0xFFF8.2004 0xFFF8.2008 0xFFF8.200C 0xFFF8.2010 0xFFF8.2014 0xFFF8.2018 0xFFF8.201C 0xFFF8.2020 0xFFF8.2024 0xFFF8.2028 0xFFF8.202C 0xFFF8.2030 0xFFF8.2034 0xFFF8.2038 0xFFF8.203C 0xFFF8.2040 0xFFF8.2044 0xFFF8.2048 0xFFF8.2100 0xFFF8.2104 0xFFF8.2108 0xFFF8.210C 0xFFF8.2110 0xFFF8.2114 0xFFF8.2118 0xFFF8.2120 0xFFF8.2124 0xFFF8.2128 0xFFF8.212C 0xFFF8.2130 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R W W W W W Source Control Register 1 Source Control Register 2 Source Control Register 3 Source Control Register 4 Source Control Register 5 Source Control Register 6 Source Control Register 7 Source Control Register 8 Source Control Register 9 Source Control Register 10 Source Control Register 11 Source Control Register 12 Source Control Register 13 Source Control Register 14 Source Control Register 15 Source Control Register 16 Source Control Register 17 Source Control Register 18 Interrupt Raw Status Register Interrupt Active Status Register Interrupt Status Register Interrupt Priority Encoding Register Interrupt Source Number Register Interrupt Mask Register Output Interrupt Status Register Mask Enable Command Register Mask Disable Command Register Source Set Command Register Source Clear Command Register End of Service Command Register 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0047 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Undefined Undefined Undefined Undefined Undefined - 38 - W90N740 Reference Manual 9. ORDERING INFORMATION PART NUMBER NAME PACKAGE DESCRIPTION W90N740CD LQFP176 176 Leads, body 22 x 22 x 1.4 mm 10. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A1 A2 March 18, 2003 May 9, 2003 1, 4 Initial Issued Add registered trademark after ARM7TDMI Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 39 - Publication Release Date: May 9, 2003 Revision A2 |
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